Narrowband physical layer (PHY) specification for 802.15.6 requires both frequency and phase modulations. In this regard, a frequency shift keying (FSK) and phase shift keying (PSK) compatible transmitter (TX) is required in the Medical Implant Communication Service/Industrial Scientific Medical (MICS/ISM) band.
Current conventional mixer based architectures can support multiple modulations, but at the expense of high circuit complexity, high power consumption and large area, in other words they are often complex, power hungry and large. Phase-locked loop (PLL) based solutions (e.g. closed loop PLL-based solutions) have emerged as suitable candidates but have limited bandwidth (BW), thus limiting achievable data rate. Despite their limited bandwidth and their ability to only provide frequency modulation, bandwidth enhancement techniques like 2-point modulation (e.g. 2 point modulation open loop type) and baseband pulse shaping techniques to generate phase modulation equivalent spectrums have helped to overcome these shortfalls. The downside to these techniques is the added complexity to the system (e.g. hardware) and baseband, and emergence of new issues like modulation gain mismatches that need to be tackled. While 2 point modulation technique has no restriction on data rate, the system is complex and careful design is required to take care of modulation gain mismatch. Furthermore, it is difficult to achieve low power using the 2-point modulation technique.
One of the existing transmitters is the conventional mixer based transmitter. The mixer based architecture adopts a conventional direct I/Q (in-phase/quadrature) modulation with up-conversion mixers. It consists of a local oscillator (LO), which is usually a phase-locked loop (PLL) that generates I/Q outputs for frequency mixing. Digital-to-analog converters (DACs) are required to control the input data to the mixers, to enable phase/frequency modulation. Hence, this architecture can provide band-shaping and support universal modulation. Such architectures consume high power typically in the range of tens of mW. Issues like I/Q mismatch adds complexity to the already complicated architecture and this makes fractional-N PLL synthesizers, as described below, a more preferred choice for transmitters.
A fractional-N PLL transmitter or architecture, having a closed loop fractional-N PLL, can consume low power in the MICS/ISM bands less than 450 MHz. However, when used in these bands, a low frequency reference has to be utilized to minimize quantization noise for good phase noise performance. This PLL loop bandwidth, which is at least 10 times smaller than the frequency reference, would be severely limited. The loop bandwidth dictates how fast the loop can switch from one frequency to another. Hence, data rate would be restricted. A larger frequency reference can be used to boost data rate but it will be at the expense of phase noise due to the increase in quantization noise. Techniques to overcome bandwidth limitation like two-point modulation exist to improve the data rate but it incurs added system complexity due to the addition of a digital-to-analogue converter (DAC) to control the voltage controlled oscillator (VCO), and the proper calibration required to minimize gain mismatch. Moreover, PLLs can only perform frequency modulation and requires baseband processing methods to generate equivalent phase modulated spectrums e.g. Gaussian Minimum Shift Keying (G/MSK).
Another conventional transmitter has an injection locked ring oscillator (RO) with hybrid edge combiner/power amplifier (EC/PA) architecture, with an open loop injection locking. The transmitter uses crystal frequency pulling for frequency modulation and employs injection locking twice, serially to 2 ring oscillators (ROs). The signal is then multiplied up 9 times to its desired frequency via an edge combiner (EC) before transmission through a power amplifier (PA) driven antenna. Through the use of a hybrid EC/PA circuit and keeping the operation of its frequency generating circuit 9 times below the desired frequency, the power consumption is in the sub-100 μW range. However, the system is very rigid as the frequency generating circuit only produces 2 fixed frequencies. It does not allow phase equivalent modulation due to its inflexible frequency selection, and neither can the frequency deviation be controlled. As a result, a low data rate of 200 kb/s for the transmitter is reported.
A further conventional transmitter is an open loop PLL based transmitter, with open loop phase rotation. Typical open loop PLL requires temporary breaking of the loop for direct frequency modulation of the VCO. This will result in frequency drifting of the VCO. For the open loop PLL based transmitter, an integer-N PLL generates 4 equally spaced clock edges and through a ΔΣ modulator controlled phase rotator (PR), it is able to generate fractional delays by performing a dithered selection among the 4 clock phases. In this case, the data rate is not limited by the PLL bandwidth because the PLL is used as a fixed multi-phase reference and frequency switching is not required. While the achievable data rate is high, it suffers from large quantization noise due to π/2 separation of each clock phase, resulting in higher in-band noise. As a result, filtering prior to the antenna is required to improve phase noise of the output.
A yet further conventional transmitter is a two-point modulated fractional-N PLL transmitter. While closed loop fractional-N has bandwidth limitation, the two-point modulation technique can be employed to enable open loop modulation. The PLL frequency can be modulated directly with an additional digital-to-analogue converter (DAC) control which has to be balanced with the appropriate fractional division ratio. In this case, frequency switching is no longer limited by the PLL bandwidth. This two-point control system proved to be a potential replacement for the mixer based architecture and is widely adopted. Although it consumes less power than a mixer based architecture, it retains the complexity with issues that need to be tackled. The system is complicated due to the delicate control required to balance the modulation gain to minimize data errors. High data rate of typically >2 Mbps can be achieved.
While open loop systems have little restriction on data rate, they cannot support phase and frequency modulation schemes concurrently.
There is therefore need for a low power single architecture that may allow frequency and phase modulations with reasonably good phase noise.